Intel's upcoming Diamond Rapids Xeon to pack 256 performance cores and a massive cache
Intel has disclosed specifications for its next-generation Diamond Rapids Xeon processors, which will feature up to 256 performance cores and a large last-level cache. Built on the 18A-P process, these chips will support AVX 10.2 instructions and adopt the UCIe-S interconnect for die-to-die communication, replacing EMIB. The announcement highlights Intel's continued push in high-core-count server CPUs.
Diamond Rapids marks a significant architectural shift for Intel's server lineup, moving memory and I/O controllers to the center of the package while distributing compute chiplets toward the edges—a layout that mirrors AMD's recent designs and could improve thermal management by reducing central hot spots. The chip relies on four base tiles fabricated on Intel 3-T, two fabric hub tiles on Intel 3, and sixteen core chiplets on the newer 18A-P node, all linked through a combination of Foveros Direct 3D stacking and UCIe-S copper connections.
Intel has not yet disclosed details on the Panther Cove core architecture itself, leaving room for additional technical deep dives before the 2027 data center release. The switch from EMIB to UCIe-S for die-to-die communication represents a notable packaging decision, as does the use of a 3D crossbar within each compute building block.
This processor could reshape data center economics for large-scale cloud and enterprise operators, who may gain higher per-socket core counts and larger caches to handle demanding workloads like AI inference and database processing. That could translate into lower power consumption per unit of compute and reduced physical server footprints, potentially benefiting organizations that manage massive infrastructure. However, adoption will depend on platform costs, software optimization, and competitive pressure from rivals, meaning the real-world impact may take years to materialize across the broader technology ecosystem.