d-Matrix's Raptor accelerator bonds compute die to custom DRAM, achieving 100 TB/s per card
At Hot Chips 2026, d-Matrix introduced Raptor, which it claims is the first 3D DRAM accelerator for generative inference. The design places a TSMC 4nm compute die face-to-face on a custom DRAM die with a 36-micron pitch, enabling 100 TB/s of memory bandwidth per card. This stacking approach aims to reduce data movement bottlenecks in AI workloads.
The Raptor design pairs a TSMC 4nm compute die with a custom DRAM die, joined face-to-face at a 36-micron pitch. This 3D stacking approach is positioned specifically for generative inference workloads, where memory bandwidth constraints often throttle performance. By bonding the logic and memory layers directly, the architecture shortens the physical distance data must travel, targeting the data movement bottleneck that commonly limits AI accelerators.
The 100 TB/s per-card figure represents a substantial bandwidth advantage over conventional accelerator designs that rely on external memory interfaces. d-Matrix presented the architecture at Hot Chips 2026, a venue known for detailed technical disclosures, suggesting the company is ready to discuss implementation specifics with the broader semiconductor engineering community.
If Raptor delivers on its bandwidth claims, it could reshape how AI inference hardware is designed, potentially lowering latency for generative applications in data centers. Organizations running large language models may see reduced infrastructure costs if fewer accelerators are needed per workload. However, the custom DRAM approach may limit manufacturing flexibility and supply chain options, which could affect adoption rates among cloud providers and enterprises evaluating long-term hardware investments.