Technology · Semiconductors · published 2026-08-26 · via Tom's Hardware

Fujitsu's Monaka server CPU uses stacked 5nm cache die and dual 256-bit SVE2 units

At Hot Chips 2026, Fujitsu revealed its 144-core Monaka server CPU, which places its entire last-level cache on a separate 5nm SRAM die stacked beneath a 2nm compute die via hybrid bonding. The chip runs dual 256-bit SVE2 vector units, a reduction from the 512-bit SVE in its predecessor, and comes in 350W air-cooled and 500W liquid-cooled variants. Evaluation samples are available now, with volume production slated for 2027.

Expanded Detail

EXPANDED:

The three-tier stack keeps 2nm silicon to under 30% of total die area, a deliberate move to accelerate time-to-market by shifting components that shrink poorly—analog voltage regulators and SRAM—onto mature 5nm nodes. Fujitsu placed the regulators directly beneath the floating-point units to support per-core dynamic voltage and frequency scaling.

Monaka's architecture contrasts with AMD's 3D V-Cache, which bonds extra SRAM atop a compute die that already carries its own L3, and more closely resembles Intel's Clearwater Forest, where cache sits

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