Samsung outlines HBM evolution toward integrated compute-in-memory at Hot Chips 2026

At Hot Chips 2026, Samsung presented a three-phase plan to evolve high-bandwidth memory into a combined memory and compute unit. The roadmap starts with moving the HBM base die to a 4nm logic process, then progressively adds logic functions, and culminates in zHBM, where DRAM stacks directly atop the processor without an interposer. This approach aims to eliminate the physical gap between memory and compute for higher bandwidth and efficiency.

Samsung's shift of the HBM base die from a DRAM process to a 4nm logic node is the foundational move enabling its roadmap. The base die previously served only as a data interface, but the more capable logic process allows it to absorb functions traditionally handled by the accelerator, reducing the XPU's workload and freeing silicon area for additional compute cores. This is the essence of the first phase, termed "XPU area reclamation."

The company's broader strategy, branded custom HBM (cHBM), keeps the conventional DRAM stack while tailoring the underlying logic to specific accelerators. This progression responds to concrete engineering pressures: TSV signaling speeds are difficult to raise, so HBM generations compensate by adding more TSVs, which consumes area and tightens pitches. HBM4 already doubled data I/O from 1,024 to 2,048 DQs, and while energy per bit improves, total power consumption continues climbing as bandwidth scales faster than efficiency gains.