Researchers Benchmark A7 CFETs Against A10 Nanosheet FETs
A team from TU Munich, the University of Modena and Reggio Emilia, and Applied Materials published a paper comparing A7 complementary FETs with A10 nanosheet FETs. Their evaluation flow connects calibrated device models, standard-cell creation, 3D parasitic extraction, an AI accelerator implementation, thermal simulation, and bias temperature instability aging analysis. By using the same device model for both options, the authors isolate how parasitic resistance and capacitance affect results at multiple design stages.
The paper comes from researchers at TU Munich, the University of Modena and Reggio Emilia, and Applied Materials. It compares A7 complementary FETs with A10 nanosheet FETs, using a co-evaluation flow that spans calibrated device models, optimized standard cells, automated GDS-to-TCAD conversion, 3D parasitic RC extraction, RTL-to-GDS AI accelerator implementation, multiphysics thermal analysis, and physics-based BTI aging evaluation.
By holding the device model constant across both technologies, the authors aim to separate the effects of parasitic resistance and capacitance from other differences. The work is listed as arXiv preprint arXiv:2609.15326, dated September 2026, and is tagged under advanced nodes, CFET, NSFET, reliability, thermal analysis, and transistor scaling.
Advances in comparing CFET and nanosheet options may influence how chipmakers choose future process nodes, affecting designers, equipment suppliers, and eventually consumers through the performance, power, and reliability of AI hardware. If such evaluations improve confidence in scaling, they could shape semiconductor roadmaps and manufacturing investment. However, benefits may take years to reach products, and thermal and aging tradeoffs could determine which applications adopt these nodes.