Siemens EDA Demonstrates PCIe 8.0 Compatibility with UCIe 3.0 for Chiplet-Based Architectures

Siemens EDA detailed how PCIe 8.0 can operate over UCIe 3.0 standardized die-to-die interconnects, enabling seamless communication across chiplet boundaries within a package. The approach delivers higher bandwidth with improved transport efficiency and greater modularity, benefiting AI, HPC, and heterogeneous compute systems that increasingly rely on multi-chip architectures. UCIe standardization allows established PCIe protocols to scale effectively in chiplet-based designs.

Chiplet-based architectures have become increasingly common as semiconductor designers seek to improve yields and modularity in complex systems. By standardizing die-to-die communication through UCIe (Universal Chiplet Interconnect Express), the industry enables established protocols like PCIe to function effectively across multiple dies within a single package. This approach addresses a fundamental challenge: traditional PCIe was designed for board-level connections, but modern systems require efficient short-reach communication between adjacent chips.

The demonstration of PCIe 8.0 compatibility with UCIe 3.0 represents a practical bridge between proven protocol infrastructure and emerging chiplet design methodologies. This compatibility allows companies developing AI accelerators, high-performance computing platforms, and heterogeneous systems to leverage existing PCIe software stacks and ecosystems while benefiting from improved bandwidth and transport efficiency in multi-chip configurations.