Researchers Optimize Clock Distribution Using Backside Metal Layers in Advanced Chip Design
UC Santa Cruz researchers have explored the use of backside clock meshes in 2-nanometer nanosheet transistor technology to improve clock signal distribution. The backside power delivery network provides additional low-resistance metal layers on the wafer's back surface that can support clock routing without consuming scarce premium routing resources on the front. This approach reduces clock skew and power consumption while maintaining the flip-flops on the frontside through through-silicon vias.
Researchers at UC Santa Cruz investigated how the unused metal layers that exist on a chip's underside—originally designed for power distribution—could serve a dual purpose in next-generation processors. By routing clock signals through these backside layers instead of competing for space on the chip's front surface, designers can free up premium routing resources while simultaneously reducing timing delays and energy consumption. The study examined this approach within OpenROAD, an open-source design tool, using a 2-nanometer nanosheet transistor process and documented how connecting backside and frontside components through specialized vertical connections preserves performance.
This optimization technique could help chipmakers navigate increasingly complex tradeoffs in advanced semiconductor manufacturing. As chip features shrink further, the scarcity of routing space becomes more acute, and any method to reduce signal delay while lowering power use may accelerate development of faster, more efficient processors. The findings may influence how semiconductor design tools and foundry technologies evolve, potentially benefiting data center operators and AI system designers who depend on power-efficient high-performance chips.