Applied Materials and Intel Expand Joint R&D for Next-Gen Chips and Packaging
Applied Materials and Intel are broadening their collaboration to speed development of transistor, interconnect, and advanced packaging technologies. The effort combines Applied's EPIC Center in Silicon Valley with Intel's Hillsboro, Oregon, R&D campus. Their work targets advanced logic nodes and Foveros-based 3D stacking for AI and high-performance computing.
Applied Materials and Intel are widening an existing alliance to shorten the path from laboratory discoveries to factory-ready processes. Their teams will work at Applied's EPIC facility in Silicon Valley and Intel's Hillsboro, Oregon, site, focusing on logic chips for AI and high-performance computing.
The joint effort covers both the front end of chipmaking and later stages such as wiring and 3D stacking. It includes Foveros-based stacking, aiming for denser connections, better power delivery, and improved heat management. Applied describes EPIC as designed to speed commercialization; Intel is a founding participant.
If successful, this collaboration could influence how quickly AI-capable chips reach data centers and devices, potentially improving performance and energy efficiency for users and cloud providers. It may also shape semiconductor workforce demand in regions hosting such R&D, while supply-chain concentration and access to advanced computing remain broader societal questions.