CXMT plans year-end launch for denser 4F² server DDR5 RDIMM
CXMT president Cao Kanyu said the company's first 4F² DRAM product will be a server DDR5 RDIMM due by the end of 2026. The design uses a vertical surrounded gate transistor to shrink each cell's footprint by about one-third compared with current 6F² cells. CXMT has not announced speeds or capacities, but it holds more than 300 patent families related to 4F² technology.
CXMT president Cao Kanyu disclosed the plan at the Integrated Chips and Chiplets Conference. The company's Vertical Surrounded Gate design wraps a gate around an upright channel, which CXMT says improves gate control and reduces leakage while shrinking cell area. CXMT has published 4F² research since 2021 and demonstrated an 8Gb full-array example at IEDM 2023.
Rivals have not yet commercialized comparable cells. Samsung presented a 16Gb 4F² design at ISSCC 2026 using vertical-channel transistors and wafer-to-wafer hybrid bonding, and reportedly has a working die, though timelines have shifted. SK hynix outlined its own 4F² vertical-gate platform at VLSI 2025.
Denser DRAM cells could eventually lower the cost per bit of server memory, which may feed into cloud and data-center pricing that businesses and consumers ultimately absorb. A Chinese supplier reaching a cell architecture its rivals have only demonstrated in research could shift competitive dynamics in a market long dominated by a few firms, potentially giving buyers more options — though without announced speeds, capacities, or pricing, any practical effect remains uncertain.