IBM, Siemens Team Up to Advance 3D Nanostack Transistor Tech

IBM and Siemens are collaborating to develop design, simulation, and lithography capabilities for IBM’s nanostack transistor architecture. Nanostack stacks nanosheet transistors vertically and can place nearly 100 billion transistors on a fingernail-sized area at the 7 angstrom node. The partnership aims to create virtual models and prepare the technology for future manufacturing generations.

IBM first introduced its nanostack transistor architecture earlier this year. The design is described as an industry-first three-dimensional nanosheet approach that stacks and offsets transistors vertically. At the 7 angstrom node, it can fit almost 100 billion transistors on a fingernail-sized area. Each stacked layer may use different materials, allowing performance and power efficiency to be tuned separately, while also supporting SRAM scaling gains.

Siemens contributes electronic design automation, process simulation, lithography optimization, and manufacturing software. The partners will build virtual models to test performance, refine designs, and identify fabrication issues before physical chips are made. IBM has already shown the architecture is viable, but more work is needed to move it toward production and future generations beyond 7 angstrom.

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