Interconnect Choices Shape Data Flow in Physical AI Systems
Physical AI systems combine multiple compute blocks that must process real-time data, make decisions, and operate within battery limits. Arteris' Ashley Stevens discusses how minimizing data movement and matching coherent interconnects to CPUs and non-coherent ones to AI accelerators can improve these designs. The article also considers future engineering challenges such as chiplets.
Physical AI designs bring together several compute blocks. These blocks must handle live data, interpret it, choose actions, and remain useful within battery constraints. A central design question is assigning processing tasks to the right block and reducing how much data travels between blocks.
Arteris’ Ashley Stevens notes that coherent interconnects suit CPUs, while non-coherent links fit AI accelerators. The discussion also points to chiplets as an upcoming engineering issue.
Better interconnect choices could affect people who rely on battery-powered autonomous devices, from vehicles to robots, by enabling more responsive and longer-running systems. Engineers and chipmakers may face pressure to balance performance with energy use, while end users could see benefits in safety and convenience if these designs mature. The impact will depend on how quickly chiplets and related approaches are adopted and validated.