SK hynix delays hybrid bonding to HBM5, cites wafer-thickness limit for AI memory stacks
SK hynix's packaging engineering VP revealed at Hot Chips 2026 that hybrid bonding will not debut until HBM5, missing HBM4E. The constraint is a 775-micron total height cap for HBM cubes, matching the standard thickness of a 300mm logic wafer, forcing thinner dies and narrower gaps. The company will continue using its MR-MUF process through Nvidia's Rubin platform, and its iHBM cooling solution cannot be retrofitted to already-designed memory generations.
The 775-micron ceiling stems from a practical co-planarity requirement: when a GPU package is ground for cold-plate attachment, both logic die and memory stacks are shaved to bare silicon, and a taller cube would protrude above the processor. SK hynix's 16-Hi HBM4, now in customer qualification at 48GB per cube, thins core dies to roughly 50 microns while halving inter-die gaps versus 12-Hi, which remains in mass production. The company's MR-MUF process will carry through Nvidia's Rubin platform, and its iHBM cooling blocks cannot be applied to memory generations already in design. JEDEC's ceiling rise from 720 to 775 microns bought time, but industry discussions now weigh 825–900 microns for 20-Hi stacks, potentially delaying hybrid bonding further.
This delay could ripple through the AI hardware supply chain, affecting data-center operators and cloud providers who depend on ever-denser memory for large-model inference. If hybrid bonding slips to HBM5, near-term performance gains may plateau, potentially slowing the pace of AI capability expansion and raising costs for enterprises training frontier models. Consumers could see indirect effects through pricing or availability of AI-powered services, though the impact would likely remain confined to specialized infrastructure markets rather than everyday devices.