Samsung Targets Doubling HBM5 Bandwidth Over HBM4E

Samsung revealed at a memory summit that its next-generation HBM5 will double the bandwidth of HBM4E and improve power efficiency by 20%. The performance jump may require a wider 4,096-bit interface rather than just faster data rates. With AI accelerators expected to pack up to 24 HBM5 stacks, total memory bandwidth could approach 100 TB/s.

The bandwidth target implies a fundamental architectural choice. Doubling per-pin data rates to 24 GT/s would strain signal integrity, while expanding the interface to 4,096 bits doubles the number of through-silicon vias, bumps, and driver circuits. Samsung's heat path block, which cuts thermal resistance by 20%, signals that thermal management is a major design constraint.

Industry projections place 20 to 24 HBM5 stacks on future AI accelerators, yielding aggregate bandwidth approaching 100 TB/s. The 4,096-bit approach has been explored by KAIST and Marvell, though JEDEC has not confirmed the specification. Power efficiency gains of 20% would likely come partly from wider, slower parallel signaling rather than faster per-pin speeds.