Chinese institute demonstrates GAA transistor fabrication using DUV lithography, but 3nm node still far off

The Institute of Microelectronics of the Chinese Academy of Sciences has built functional stacked-nanosheet gate-all-around transistors using immersion DUV lithography, avoiding the need for EUV scanners. The devices show acceptable on/off current ratios, but the institute has not disclosed key dimensions like gate pitch or metal pitch, and the process is far from a complete 3nm manufacturing node. This marks progress in China's independent semiconductor development, though commercial 3nm-class production remains years away.

The demonstration centers on stacked-nanosheet GAA transistors, a structure that wraps the gate around multiple silicon sheets to improve electrical control at tiny scales. IMECAS used immersion DUV lithography, a mature technique, rather than EUV scanners, which are restricted from sale to China. The reported on/off ratios, around 9.7×10⁵ and 7.6×10⁵, pass a basic threshold for functional switching, but the institute withheld gate pitch, metal pitch, and density figures, leaving no basis for direct comparison with commercial 3nm nodes.

This work builds on IMECAS’s research since 2020 into sub-3nm transistor architectures. It validates a possible DUV-based path for future advanced chips, yet the process remains an early integration experiment, not a manufacturable flow. Without disclosed dimensions or yield data, the gap to a full 3nm node—including interconnects, SRAM, and packaging—remains substantial.