Synopsys and TSMC Expand Collaboration for AI Chip Design with Certified Flows
Synopsys and TSMC announced new innovations to speed development of next-generation AI and high-performance computing systems, including A14 process certification and agentic AI capabilities in EDA flows. The partnership enables multi-die design flows and advanced packaging with silicon-proven IP, helping customers manage growing design complexity. The joint efforts aim to accelerate adoption of TSMC's latest process technologies and improve design convergence.
The collaboration centers on TSMC's A14 process node, with Synopsys securing certification across digital and analog design flows, including a newly achieved device routing milestone for analog place-and-route automation. Both companies are integrating agentic AI into their EDA tools—Custom Compiler for analog migration and Fusion Compiler with LLM-assisted analysis—to automate complex workflows and reduce manual intervention.
Beyond traditional chip design, the partnership addresses advanced packaging challenges. Synopsys' 3DIC Compiler platform now supports integrated voltage regulator co-design on TSMC's CoWoS technology and enables co-packaged optics design on TSMC's COUPE technology, combining photonic and electronic co-design for high-speed optical interconnects in next-generation AI systems.
This partnership could meaningfully shorten development cycles for AI and high-performance computing chips, potentially accelerating the pace of AI hardware innovation across industries that depend on advanced semiconductors—from cloud computing to autonomous vehicles. Smaller design teams may gain access to automated workflows that previously required specialized expertise, lowering barriers to entry. However, the concentration of advanced chip design capabilities within a few major players could intensify competitive pressures on smaller semiconductor firms, potentially shaping market dynamics and technology access in ways that affect downstream consumers and businesses alike.