Cadence and TSMC Deepen Collaboration for Advanced AI Chip Design
Cadence announced an expanded partnership with TSMC, achieving tool certification for TSMC's A14 process and introducing silicon-proven IP for N3P and N2P technologies. The collaboration enables agentic AI and 3D-IC design flows across TSMC's N3, N2, A16, and A14 processes, including support for wafer-scale systems with hundreds of chiplets. The companies aim to help customers achieve faster time-to-market and improved performance, power, and area on leading-edge nodes.
The certification covers Cadence's digital, signoff, and custom/analog flows for TSMC's A16 and A14 nodes, with the Virtuoso Studio suite reportedly cutting design iterations by up to 2.5 times. On the IP side, UCIe-64G has been taped out on A14, while DDR5, LPDDR5, and PCIe 6.0 IP are taped out on N2P. The partnership also extends to 3D-IC packaging, supporting wafer-scale systems with hundreds of chiplets and advanced CoWoS-L-style packages, with Artisan Foundation IP for A14 expected in late 2026.
This collaboration could accelerate the development of AI and high-performance computing chips, potentially lowering costs and time-to-market for companies building next-generation systems. Consumers may see faster, more energy-efficient AI applications in areas like autonomous vehicles, data centers, and mobile devices. However, the concentration of advanced chip design capabilities among a few firms could also raise barriers for smaller players, potentially shaping competitive dynamics in the semiconductor industry.