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Technology · Semiconductors · published 2026-10-09 · via Semiengineering.com

Weekly Chip Roundup: Foundry Deal, R&D Expansion, and 2nm Ecosystem

Image via Semiengineering.com
Image via Semiengineering.com

The weekly roundup highlighted a $2 billion foundry arrangement in which GlobalFoundries will produce silicon interposers for TSMC's CoWoS packaging line in New York, with volume output targeted for early 2028. It also covered expanded Applied Materials-Intel R&D on transistors, interconnects, and packaging; Rapidus's new 2nm ecosystem with 17 design partners; and a Xanadu-GlobalFoundries photonics manufacturing tie-up. Other items included a conditional $1.5 billion U.S. financing package for Wolfspeed and industry attention on AI chips, data-center construction, SiC, chip smuggling, 800V power, quantum hardware, and wireless EV charging.

Expanded Detail

The week’s largest manufacturing item was a $2 billion arrangement: GlobalFoundries will make silicon interposers for TSMC’s CoWoS packaging ecosystem at its Malta, New York site, with volume output targeted for early 2028. Applied Materials and Intel also widened their joint R&D to cover next-generation transistors, interconnects, and advanced packaging, linking work in Silicon Valley and Hillsboro, Oregon.

Rapidus introduced Rapidus CORE, a framework to guide customers from design through production for its planned 2nm foundry, starting with 17 design-service partners. Xanadu and GlobalFoundries agreed to move ultra-low-loss silicon nitride photonics and superconducting nanowire single-photon detectors onto a 300mm line in Malta. Wolfspeed received a conditional U.S. financing package of up to $1.5 billion over 30 years to expand SiC and wide-bandgap power-device output.

Count: first para ~50? Let's count. "The week’s largest manufacturing item was a $2 billion arrangement: GlobalFoundries will make silicon interposers for TSMC’s CoWoS packaging ecosystem at its Malta, New York site, with volume output targeted for early 2028. Applied Materials and Intel also widened their joint R&D to cover next-generation transistors, interconnects, and advanced packaging, linking work in Silicon Valley and Hillsboro, Oregon." Count: The1 week’s2 largest3 manufacturing4 item5 was6 a7 $2 8 billion9 arrangement10 GlobalFoundries11 will12 make13 silicon14 interposers15 for16 TSMC’s17 CoWoS

Context

These moves could reinforce advanced packaging, 2nm design, photonics, and SiC supply chains, potentially affecting chip designers, equipment makers, data-center operators, automakers, and consumers through availability, cost, and energy efficiency. Regional hubs in New York, Oregon, and Silicon Valley may see more specialized jobs and investment, though outcomes depend on execution, demand, and policy stability. The AI buildout may amplify benefits while also concentrating attention and resources on leading-edge and power technologies. Count: These1 moves2 could3 reinforce4 advanced5 packaging6 2nm7 design8 photonics9 and10 SiC11 supply12 chains13 potentially14 affecting15 chip16 designers17 equipment18 makers19 data-center20 operators21 automakers22 and23 consumers24 through25 availability26 cost27 and28 energy29 efficiency30. Regional31 hubs32 in33 New34 York35 Oregon36 and37 Silicon38 Valley39 may40 see41 more42 specialized43 jobs44 and45 investment46 though47 outcomes48 depend49

Expanded detail and Context are AI-generated analysis; the linked article remains the authoritative source.
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This summary is Al-enhanced to contain extended analysis and broader social context. The original is {NAME); the linked article is the authoritative source. Original headline: “Chip Industry Week In Review.” Browse more stories.